SH7751 Datasheet, PDF (175/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Memory Management Unit (MMU)
of an access to an area other than the P4 area, the accessed virtual address is translated to a
physical address. If the virtual address belongs to the P1 or P2 area, the physical address is
uniquely determined without accessing the TLB. If the virtual address belongs to the P0, U0, or P3
area, the TLB is searched using the virtual address, and if the virtual address is recorded in the
TLB, a TLB hit is made and the corresponding physical address is read from the TLB. If the
accessed virtual address is not recorded in the TLB, a TLB miss exception is generated and
processing switches to the TLB miss exception handling routine. In the TLB miss exception
handling routine, the address translation table in external memory is searched, and the
corresponding physical address and page management information are recorded in the TLB. After
the return from the exception handling routine, the instruction which caused the TLB miss
exception is re-executed.
3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode
There are two virtual memory systems, single virtual memory and multiple virtual memory, either
of which can be selected with the MMUCR.SV bit. In the single virtual memory system, a number
of processes run simultaneously, using virtual address space on an exclusive basis, and the
physical address corresponding to a particular virtual address is uniquely determined. In the
multiple virtual memory system, a number of processes run while sharing the virtual address
space, and a particular virtual address may be translated into different physical addresses
depending on the process. The only difference between the single virtual memory and multiple
virtual memory systems in terms of operation is in the TLB address comparison method (see
section 3.4.3, Address Translation Method).
3.3.7 Address Space Identifier (ASID)
In multiple virtual memory mode, the 8-bit address space identifier (ASID) is used to distinguish
between processes running simultaneously while sharing the virtual address space. Software can
set the ASID of the currently executing process in PTEH in the MMU. The TLB does not have to
be purged when processes are switched by means of ASID.
In single virtual memory mode, ASID is used to provide memory protection for processes running
simultaneously while using the virtual memory space on an exclusive basis.
Notes: 1. In single virtual memory mode of the SH-4, entries with the same virtual page number
(VPN) but different ASIDs cannot be set in the TLB simultaneously.
2. When the SH7751 is operating in single virtual memory mode and user mode, the LSI
may hang during hardware ITLB miss handling (see section 3.5.4, Hardware ITLB
Miss Handling), or an ITLB multiple hit exception may occur, if an ITLB miss occurs
and the UTLB contains address translation information including an ITLB miss address
Rev.4.00 Oct. 10, 2008 Page 77 of 1122
REJ09B0370-0400