SH7751 Datasheet, PDF (477/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Bits 15 to 13—Write Precharge Delay (TRWL2–TRWL0): These bits set the synchronous
DRAM write precharge delay time. In auto-precharge mode, they specify the time until the next
bank active command is issued after a write cycle. After a write cycle, the next active command is
not issued for a period set by TPC[2:0] and TRWL[2:0] bits*. In RAS down mode, they specify
the time until the next precharge command is issued. After a write cycle, the next precharge
command is not issued for a period of TRWL. This setting is valid only when synchronous DRAM
interface is set.
Note: * For setting values and the period during which no command is issued, see 23.3.3, Bus
Timing.
Bit 15: TRWL2 Bit 14: TRWL1 Bit 13: TRWL0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Note: * Inhibited in RAS down mode
Write Precharge ACT Delay Time
1 (Initial value)
2
3*
4*
5*
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Rev.4.00 Oct. 10, 2008 Page 379 of 1122
REJ09B0370-0400