SH7751 Datasheet, PDF (710/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
SCSCR1 can be read or written to by the CPU at all times.
SCSCR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt
(TXI) request generation when serial transmit data is transferred from SCTDR1 to SCTSR1 and
the TDRE flag in SCSSR1 is set to 1.
Bit 7: TIE
Description
0
Transmit-data-empty interrupt (TXI) request disabled*
(Initial value)
1
Transmit-data-empty interrupt (TXI) request enabled
Note: * TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it
to 0, or by clearing the TIE bit to 0.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI)
request and receive-error interrupt (ERI) request generation when serial receive data is transferred
from SCRSR1 to SCRDR1 and the RDRF flag in SCSSR1 is set to 1.
Bit 6: RIE
Description
0
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI)
request disabled*
(Initial value)
1
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI)
request enabled
Note: * RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF flag, or the
FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5: TE
Description
0
Transmission disabled*¹
(Initial value)
1
Transmission enabled*²
Notes: 1. The TDRE flag in SCSSR1 is fixed at 1.
2. In this state, serial transmission is started when transmit data is written to SCTDR1 and
the TDRE flag in SCSSR1 is cleared to 0.
SCSMR1 setting must be performed to decide the transmit format before setting the TE
bit to 1.
Rev.4.00 Oct. 10, 2008 Page 612 of 1122
REJ09B0370-0400