SH7751 Datasheet, PDF (206/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
• U bit (dirty bit)
The U bit is set to 1 if data is written to the cache line while the cache is being used in copy-
back mode. That is, the U bit indicates a mismatch between the data in the cache line and the
data in external memory. The U bit is never set to 1 while the cache is being used in write-
through mode, unless it is modified by accessing the memory-mapped cache (see section 4.5,
Memory-Mapped Cache Configuration (SH7751) and 4.6, Memory-Mapped Cache
Configuration (SH7751R)). The U bit is initialized to 0 by a power-on reset, but retains its
value in a manual reset.
• Data field
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
• LRU (SH7751R only)
In a 2-way set-associative system, up to two entry addresses can register the same data in
cache. The LRU bit indicates to which way the entry is to be registered among the two ways.
There is one LRU bit in each entry, and it is controlled by hardware. The LRU (Last Recently
Used) algorithm that selects the most recently accessed way is used for way selection. The
LRU bit is initialized to 0 by a power-on reset, but is not initialized by a manual reset. The
LRU bit cannot be read from or written to by software.
4.3.2 Read Operation
When the OC is enabled (CCR.OCE = 1) and data is read by means of an effective address from a
cacheable area, the cache operates as follows:
1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5].
2. The tag is compared with bits [28:10] of the address resulting from effective address
translation by the MMU:
• If the tag matches and the V bit is 1
→ (3a)
• If the tag matches and the V bit is 0
→ (3b)
• If the tag does not match and the V bit is 0
→ (3b)
• If the tag does not match, the V bit is 1, and the U bit is 0 → (3b)
• If the tag does not match, the V bit is 1, and the U bit is 1 → (3c)
3a. Cache hit
The data indexed by effective address bits [4:0] is read from the data field of the cache line
indexed by effective address bits [13:5] in accordance with the access size
(quadword/longword/word/byte).
Rev.4.00 Oct. 10, 2008 Page 108 of 1122
REJ09B0370-0400