SH7751 Datasheet, PDF (559/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
SA2
SA1
SA0
Description
0
0
0
Reserved (Setting prohibited)
1
Dynamic I/O bus sizing
1
0
8-bit I/O space
1
16-bit I/O space
1
0
0
8-bit common memory
1
16-bit common memory
1
0
8-bit attribute memory
1
16-bit attribute memory
When the MMU is on, wait cycles in a bus access can be set in MMU page units. See section 3,
Memory Management Unit (MMU), for details of the setting method. When the MMU is off,
access is always performed according to the setting of the TC bit in PTEA. When TC is cleared to
0, bits A5W2–A5W0 in wait control register 2 (WCR2) and bits A5PCW1–A5PCW0, A5TED2–
A5TED0, and A5TEH2–A5TEH0 in the PCMCIA control register (PCR) are selected. When TC
is set to 1, bits A6W2–A6W0 in WCR2 and bits A6PCW1–A6PCW0, A6TED2–A6TED0, and
A6TEH2–A6TEH0 in PCR are selected.
Access to a PCMCIA interface area by the DMAC is always performed using the DMAC's
CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values.
AnPCW1–AnPCW0 specify the number of wait states to be inserted in a low-speed bus cycle; a
value of 0, 15, 30, or 50 can be set, and this value is added to the number of wait states for
insertion specified by WCR2. AnTED2–AnTED0 can be set to a value from 0 to 15, enabling the
address, CS, CE2A, CE2B, and REG setup times with respect to the RD and WE1 signals to be
secured. AnTEH2–AnTEH0 can also be set to a value from 0 to 15, enabling the address, CS,
CE2A, CE2B, and REG data hold times with respect to the RD and WE1 signals to be secured.
Wait cycles between cycles are set with bits A5IW2–A5IW0 and A6IW2–A6IW0 in wait control
register 1 (WCR1). The inter-cycle write cycles selected depend only on the area accessed (area 5
or 6): when area 5 is accessed, bits A5IW2–A5IW0 are selected, and when area 6 is accessed, bits
A6IW2–A6IW0 are selected.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed in wraparound mode on the data at the 32-byte boundary. The bus is not
released during this operation.
Rev.4.00 Oct. 10, 2008 Page 461 of 1122
REJ09B0370-0400