SH7751 Datasheet, PDF (350/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Power-Down Modes
Bit
Description
CSTP2
0
Peripheral clock is supplied to PCIC
1
Peripheral clock supply to PCIC is stopped
CSTP1
0
Peripheral clock is supplied to TMU channels 3 and 4
1
Peripheral clock supply to TMU channels 3 and 4 is stopped
CSTP0
0
INTC detects PCIC and TMU channel 3 and 4 interrupts
1
INTC does not detect PCIC and TMU channel 3 and 4 interrupts
MSTP6
0
SQ operates
1
Clock supplied to SQ is stopped
MSTP5
0
1
UBC operates
Clock supplied to UBC is stopped*³
MSTP4
0
1
DMAC operates
Clock supplied to DMAC is stopped*⁴
MSTP3
0
SCIF operates
1
Clock supplied to SCIF is stopped
MSTP2
0
1
TMU operates
Clock supplied to TMU is stopped, and register is initialized*¹
MSTP1
0
1
RTC operates
Clock supplied to RTC is stopped*²
MSTP0
0
SCI operates
1
Clock supplied to SCI is stopped
Notes: 1. The register initialized is the same as in standby mode, but initialization is not
performed if the RTC clock is not in use (see section 12, Timer Unit (TMU)).
2. The counter operates when the START bit in RCR2 is 1 (see section 11, Realtime
Clock (RTC)).
3. For details, see section 20.6, User Break Controller Stop Function.
4. Terminate DMA transfers prior to making the transition to module standby mode. If you
make a transition to module standby mode while DMA transfers are in progress, the
results of those transfers cannot be guaranteed.
9.7.2 Exit from Module Standby Function
In the case of the standby control register and standby control register 2, the module standby
function is exited by writing 0 to the MSTP6–MSTP0 bits. In the case of clock stop register 00,
the module standby function is exited by writing 1 to the corresponding bit in clock stop clear
register 00.
Rev.4.00 Oct. 10, 2008 Page 252 of 1122
REJ09B0370-0400