SH7751 Datasheet, PDF (902/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. User Break Controller (UBC)
Break data register B (BDRB) is a 32-bit readable/writable register that specifies the data (bits 31–
0) to be used in the channel B break conditions. BDRB is not initialized by a power-on reset or
manual reset.
Bits 31 to 0—Break Data B31 to B0 (BDB31–BDB0): These bits hold the data (bits 31–0) to be
used in the channel B break conditions.
20.2.10 Break Data Mask Register B (BDMRB)
Bit: 31
30
29
28
27
26
25
24
BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24
Initial value:
*
*
*
*
*
*
*
*
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 23
22
21
20
19
18
17
16
BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16
Initial value:
*
*
*
*
*
*
*
*
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 15
14
13
12
11
10
9
BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9
Initial value:
*
*
*
*
*
*
*
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
BDMB8
*
R/W
Bit:
7
BDMB7
Initial value:
*
R/W: R/W
Note: * Undefined
6
BDMB6
*
R/W
5
BDMB5
*
R/W
4
BDMB4
*
R/W
3
BDMB3
*
R/W
2
BDMB2
*
R/W
1
BDMB1
*
R/W
0
BDMB0
*
R/W
Break data mask register B (BDMRB) is a 32-bit readable/writable register that specifies which
bits of the break data set in BDRB are to be masked. BDMRB is not initialized by a power-on
reset or manual reset.
Rev.4.00 Oct. 10, 2008 Page 804 of 1122
REJ09B0370-0400