SH7751 Datasheet, PDF (13/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page Revision (See Manual for Details)
4.2 Register
104
Description amended
Descriptions
When the OC is enabled (OCE = 1), the ORA bit specifies
• ORA: OC RAM
whether the half of the OC are to be used as RAM. When the
enable bit*³
OC is not enabled (OCE = 0), the ORA bit should be cleared to
0.
0: Normal mode (the entire OC is used as a cache)
1: RAM mode (half of the OC is used as a cache and the other
half is used as RAM)
4.3.1 Configuration 108
LRU (SH7751R only)
Description deleted
In a 2-way set-associative system, up to two entry addresses
can register the same data in cache.
4.3.10 Notes on Using 114 to
OC RAM Mode
116
(SH7751R Only) when
in Cache Enhanced
Mode
Newly added
4.4.1 Configuration 119
LRU (SH7751R only)
Description deleted
In a 2-way set-associative system, up to two entry addresses
can register the same data in cache.
4.7 Store Queues
131, 132 Description added
Note that power-down modes (STBCR2.MSTP6 = 1) that stop
SQ functions cannot be used on the SH7751 when using the
operand cache for write-back operations.*
Note: * Cases where write-back operations are performed:
• When the operand cache is used in copy-back
mode (determined by the CCR.CB and
CCR.WT bits and, if address translation is
performed, the WT bit in the page management
information)
• When the memory allocation cache function is
used to write to the OC address array, and an
entry is generated when both the V and U bits
are set to 1
4.7.6 SQ Usage Notes 134
(SH7751R only)
Title amended
Rev.4.00 Oct. 10, 2008 Page xiii of xcviii
REJ09B0370-0400