SH7751 Datasheet, PDF (556/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
CKIO
T1 TB2 TB1 TB2 TB1 TB2 TB1 T2
A25–A5
A4–A0
CSn
RD/WR
RD
D31–D0
(read)
BS
RDY
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.41 Burst ROM Basic Access Timing
Rev.4.00 Oct. 10, 2008 Page 458 of 1122
REJ09B0370-0400