SH7751 Datasheet, PDF (603/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)
Bit: 31
30
29
28
27
26
25
24
Initial value: —
—
—
—
—
—
—
—
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 23
0
·············································
Initial value: —
·············································
—
R/W: R/W
·············································
R/W
DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit readable/writable registers that
specify the destination address of a DMA transfer. These registers have a counter feedback
function, and during a DMA transfer they indicate the next destination address. In single address
mode, the DAR value is ignored when a device with DACK has been specified as the transfer
destination.
Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64-
bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will
be detected and the DMAC will halt.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode, sleep mode, and deep sleep mode.
Notes: 1. When a 16-bit, 32-bit, 64-bit, or 32-byte boundary address is specified, take care with
the setting of bit 0, bits 1–0, bits 2–0, or bits 4–0, respectively. If an address
specification that ignores boundary considerations is made, the DMAC will detect an
address error and halt operation on all channels (DMAOR: address error flag AE = 1).
The DMAC will also detect an address error and halt if an area 7 address is specified in
an external data bus transfer, or if the address of a nonexistent on-chip peripheral
module is specified.
2. External addresses are 29 bits in length. SAR[31:29] and DAR[31:29] are not used in
DMA transfer, and it is recommended that they both be set to 000.
Rev.4.00 Oct. 10, 2008 Page 505 of 1122
REJ09B0370-0400