SH7751 Datasheet, PDF (905/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. User Break Controller (UBC)
Bit 6—PC Break Select B (PCBB): Specifies whether a channel B instruction access cycle break
is to be effected before or after the instruction is executed. This bit is not initialized by a power-on
reset or manual reset.
Bit 6: PCBB
0
1
Description
Channel B PC break is effected before instruction execution
Channel B PC break is effected after instruction execution
Bits 5 and 4—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 3—Sequence Condition Select (SEQ): Specifies whether the conditions for channels A and B
are to be independent or sequential. This bit is not initialized by a power-on reset or manual reset.
Bit 3: SEQ
0
1
Description
Channel A and B comparisons are performed as independent conditions
Channel A and B comparisons are performed as sequential conditions
(channel A → channel B)
Bits 2 and 1—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 0—User Break Debug Enable (UBDE): Specifies whether the user break debug function (see
section 20.4, User Break Debug Support Function) is to be used.
Bit 0: UBDE
0
1
Description
User break debug function is not used
User break debug function is used
(Initial value)
Rev.4.00 Oct. 10, 2008 Page 807 of 1122
REJ09B0370-0400