SH7751 Datasheet, PDF (1036/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
case of memory write, the internal control allows only the writing of valid byte lane data to the
local bus. Only the linear mode is supported for addressing for burst transfers, and the 2 least
significant bits of the PCI address are regarded as B'00.
If a memory read line command or memory read multiple command is received, they operate as
memory reads. Similarly, when a memory write invalidate command is received, it functions as a
memory write.
Data must be set in the following registers prior to performing target transfers using memory read
or memory write commands: PCI configuration register 5 (PCICNF5), PCI configuration register
6 (PCICNF6), PCI local space register 0 (PCILSR [0]), PCI local space register 1 (PCILSR [1]),
PCI local address register 0 (PCILAR [0]), and PCI local address register 1 (PCILAR [1]).
31
PCICONF5
(PCICONF6)
20 19
0
31
PCI address
0
PCIC access adjudication
31 28
20 19
0
PCILSR0
(PCILSR1)
000001111
31 28
20 19
0
PCILAR0
(PCILAR1)
31 28
0
Local address
Figure 22.4 Local Address Space Accessing Method
The PCIC supports two local address spaces (address space 0 and address space 1).
A certain range of the address space on the PCI bus corresponds to the local address space.
The local address space 0 is controlled by the PCICONF5, PCILAR0 and PCISR0. Figure 22.4
shows the method of accessing the local address space.
Rev.4.00 Oct. 10, 2008 Page 938 of 1122
REJ09B0370-0400