SH7751 Datasheet, PDF (54/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page Revision (See Manual for Details)
Appendix A Address 1077 to
List
1084
Table A.1 Address List
Synchronization Clock
Iclk → Ick
Bclk → Bck
Pclk → Pck
1078
Table amended
Module Register
Area 7
P4 Address Address*¹
PCIC PCICR
H'FE20 0100 H'1E20 0100
*²
Appendix B Package
Dimensions
Figure B.3 Package
Dimensions (256-pin
BGA)
1087
Newly added
Appendix C Mode Pin 1089
Settings
Table C.1 Clock
Operating Modes
(SH7751)
Table amended and notes added
External
Pin Combination
Frequency
(vs. Input Clock)
Clock
Operating
Mode
MD2
1/2
Peripheral
Frequency
CPU Bus Module
MD1 MD0 Divider
PLL1 PLL2 Clock Clock Clock
0
0
0
0
Off
On On 6
3/2 3/2
1
1
Off
On On 6
1
1
2
1
0
On
On On 3
1
1/2
3
1
Off
On On 6
2
1
4
1
0
0
On
On On 3
3/2 3/4
5
1
Off
On On 6
3
3/2
6
1
0
Off
Off Off 1
1/2 1/2
FRQCR
Initial Value
H'0E1A
H'0E23
H'0E13
H'0E13
H'0E0A
H'0E0A
H'0808
Table C.7 PCI Mode 1091
Notes: 1. The multiplication factor of 1/2 frequency driver is
solely determined by the clock operating mode.
2. For the ranges input clock frequency, see the
description of the EXTAL clock input frequency (f_EX)
and the CKIO clock output (f_OP) in section 23.3.1,
Clock and Control Signal Timing.
Table amended
Mode
0
1
Pin Value
MD10
MD9
0
0
0
1
Mode
PCI host with external clock input
PCI host with feedback input clock from CKIO
Rev.4.00 Oct. 10, 2008 Page liv of xcviii
REJ09B0370-0400