SH7751 Datasheet, PDF (895/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. User Break Controller (UBC)
Table 20.1 shows the UBC registers.
Table 20.1 UBC Registers
Name
Area 7
Abbreviation R/W Initial Value P4 Address Address
Access
Size
Break address BARA
register A
R/W Undefined H'FF200000 H'1F200000 32
Break address
mask
register A
BAMRA
R/W Undefined H'FF200004 H'1F200004 8
Break bus
BBRA
cycle register A
R/W H'0000
H'FF200008 H'1F200008 16
Break ASID
register A
BASRA
R/W Undefined H'FF000014 H'1F000014 8
Break address BARB
register B
R/W Undefined H'FF20000C H'1F20000C 32
Break address
mask
register B
BAMRB
R/W Undefined H'FF200010 H'1F200010 8
Break bus
BBRB
cycle register B
R/W H'0000
H'FF200014 H'1F200014 16
Break ASID
register B
BASRB
R/W Undefined H'FF000018 H'1F000018 8
Break data
register B
BDRB
R/W Undefined H'FF200018 H'1F200018 32
Break data
BDMRB
mask register B
R/W Undefined H'FF20001C H'1F20001C 32
Break control
register
BRCR
R/W H'0000*
H'FF200020 H'1F200020 16
Note: * Some bits are not initialized. See section 20.2.12, Break Control Register (BRCR), for
details.
Rev.4.00 Oct. 10, 2008 Page 797 of 1122
REJ09B0370-0400