SH7751 Datasheet, PDF (608/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
Bit 19—DREQ Select (DS): Specifies either low level detection or falling edge detection as the
sampling method for the DREQ pin used in external request mode.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR0–CHCR3.
Bit 19: DS
Description
0
Low level detection
1
Falling edge detection
Notes: Level detection burst mode when TM = 1 and DS = 0
Edge detection burst mode when TM = 1 and DS = 1
(Initial value)
Bit 18—Request Check Level (RL): Selects whether the DRAK signal (that notifies an external
device of the acceptance of DREQ) is an active-high or active-low output.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. It is invalid in DDT mode.
Bit 18: RL
0
1
Description
DRAK is an active-high output
DRAK is an active-low output
(Initial value)
Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the
data read cycle or write cycle. In single address mode, DACK is always output regardless of the
setting of this bit.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR1–CHCR3. (DDT mode: TDACK)
Bit 17: AM
0
1
Description
DACK is output in read cycle
DACK is output in write cycle
(Initial value)
Rev.4.00 Oct. 10, 2008 Page 510 of 1122
REJ09B0370-0400