SH7751 Datasheet, PDF (1070/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
External Input Pin (PCICLK) Operating Mode: In this mode the PCI bus clock is input from
outside. This mode requires the provision of an external oscillation module for the PCI.
CKIO Operating Mode: In this mode, the clock output from the CKIO pin is used as the PCI bus
clock. The feedback input from the CKIO pin is used as the PCI bus clock.
This mode can only be used when the PCIC is operating as the host bridge. It cannot be used in
non-host mode.
When using this mode, note the CKIO load capacitance and only use it within the prescribed load
stated in the manual. Note, too, that the clock frequency of CKIO cannot be guaranteed until the
PLL oscillation stabilizes after a power-on reset or the clock frequency is changed. Also, in
standby mode, the clock stops. This mode should only be employed after checking that these
points do not cause any problems from the viewpoint of the system configuration.
In CKIO operating mode, the maximum Bck frequency is 66 MHz.
When not using the PCICLK pin, fix the pin level high.
66 MHz Compatibility: The PCIC is not necessarily fully compatible with the 66 MHz bus
standard of the PCI. For details, see section 23, Electrical Characteristics. In the electrical
characteristics of the PCI bus-related pins, the permissible delay on the board is extremely short.
For this reason, the on-board load capacitance and impedance matching should be considered
before connecting to a 66MHz-compatible PCI device. Note, too, that only one PCI device can be
connected.
In the PCI standard, there are two methods for checking if a PCI device can operate at 66 MHz:
checking the 66 MHz operating status in the configuration register 1, and monitoring the M66ENB
pin in the PCI bus standard. The PCIC supports the 66 MHz operating status (66M) bit of the
configuration register 1 (PCICONF1). The PCIC does not have a special pin for directly
monitoring the M66ENB pin. Also, there is no control output pin for switching between 33 MHz
and 66 MHz when an external oscillator is used. A special external circuit is required to effect
these controls.
22.9 Power Management
22.9.1 Power Management Overview
The PCIC supports the PCI power management (version 1.0 compatible) configuration registers.
These are as follows:
Rev.4.00 Oct. 10, 2008 Page 972 of 1122
REJ09B0370-0400