SH7751 Datasheet, PDF (1000/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM)
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
MST_BRKN TGT_BUSTO MST_BUSTO
—
—
—
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: R
R
R/W
R/W
R/W
R
R
R
PP Bus-R/W: R
R
R/W
R/W
R/W
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
TGT_ABORT MST_ABORT DPERR_WT DPERR_RD
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R/W
R/W
R/W
R/W
PP Bus-R/W: R
R
R
R
R/W
R/W
R/W
R/W
The PCI arbiter interrupt mask register (PCIAINTM) sets interrupt masks for the individual
interrupts that occur due to errors generated during PCI transfers performed by other PCI devices
when the PCIC is operating as the host with the arbitration function. It is a 32-bit register that is
readable and writable from both the peripheral bus and the PCI bus. Each bit is set to 0 to disable
the respective interrupt, or 1 to enable that interrupt.
The PCIINTM register is initialized to H'00000000 at a power-on reset or software reset.
Bits 31 to 14—Reserved: These bits always return 0 when read. Always write 0 to these bits
when writing.
Rev.4.00 Oct. 10, 2008 Page 902 of 1122
REJ09B0370-0400