SH7751 Datasheet, PDF (1028/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
22.3.3 PCIC Initialization
After a power-on reset, the configuration register initialization bit (CFINIT) of the PCI control
register (PCICR) is cleared. At this point, if the PCIC is operating as the PCI bus host, the bus
privileges are permanently granted to the PCIC, and no device arbitration is performed on the PCI
bus. When the PCIC is not operating as host, retries are returned without accepting access from
PCI devices connected to the PCI bus.
The PCIC's internal configuration registers and local registers must be initialized while the
CFINIT bit is cleared to 0. On completion of initialization, set the CFINIT bit to 1. When
operating as host, arbitration is enabled; when operating as non-host, the PCIC can be accessed
from the PCI bus.
Regardless of whether or not the PCIC is operating as host, external PCI devices cannot be
accessed from the PCIC while the CFINIT bit is cleared. If the PCIC's internal configuration
registers and local registers are initialized correctly, the PCIC will operate correctly. However, we
recommend first setting the CFINIT bit to 1.
When the PCIC is operating as the host, arbitration is enabled. When operating as non-host, the
PCIC can be accessed from the PCI bus.
Regardless of whether the PCIC is operating as the host or non-host, external PCI devices cannot
be accessed from the PCIC while the CFINT bit is being cleared. Set the CFINIT bit to 1 before
accessing an external PCIC device.
Be sure to initialize the following 13 registers while the CFINIT bit is being cleared: configuration
registers 1, 2, 11 (PCICONF1, 2, 11) for PCI, local space registers 0, 1 (PCILSR0, 1) for PCI,
local address registers 0, 1 (PCILAR0, 1) for PCI, PCI bus control registers 1, 2 (PCIBCR1, 2) for
PCIC-BSC, PCI weight control registers 1, 2, 3 (PCIWCR1, 2, 3), and PCI-specific memory
control register (PCIMCR). Since the PCIC-BSC is fixed in sleep mode at a power-on reset
regardless of the value of the external pin (MD7) for master/slave designation, do not make a
PCIC-BSC register setting that is prohibited in the sleep mode.
Also, as the BSC has BCR1.BREQEN bits that enable an external request and a bus request from
the PCIC to be accepted, BCR1.BREQEN should be set to 1 when the PCIC is used.
While 1 is being set in the CFINIT bit, the registers for the PCIC-BSC (PCIBCR1, 2, PCIWCR1,
2, 3, PCIMCR) cannot be written to. The data transfer accuracy between the PCI bus and local bus
cannot be guaranteed if an attempt is made to write to any of these registers during this period.
Rev.4.00 Oct. 10, 2008 Page 930 of 1122
REJ09B0370-0400