SH7751 Datasheet, PDF (85/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 22.12 Target Write Cycle in Non-Host Mode (Single) .................................................... 954
Figure 22.13 Target Memory Read Cycle in Host Mode (Burst) ................................................ 955
Figure 22.14 Target Memory Write Cycle in Host Mode (Burst) ............................................... 956
Figure 22.15 Master Memory Write Cycle in Host Mode (Burst, With Stepping)...................... 957
Figure 22.16 Target Memory Read Cycle in Host Mode (Burst, With Stepping) ....................... 958
Figure 22.17 Endian Conversion Modes for Peripheral Bus ....................................................... 959
Figure 22.18 Peripheral Bus ↔ PCI Bus Data Alignment .......................................................... 960
Figure 22.19 Endian Control for Local Bus................................................................................. 961
Figure 22.20 Data Alignment at DMA Transfer.......................................................................... 962
Figure 22.21 (1) Data Alignment at Target Memory Transfer (Big-Endian Local Bus) ............ 964
Figure 22.21 (2) Data Alignment at Target Memory Transfer (Little-Endian Local Bus) ......... 965
Figure 22.22 Data Alignment at Target I/O Transfer (Both Big Endian and Little Endian) ....... 966
Figure 22.23 Data Alignment at Target Configuration Transfer
(Both Big Endian and Little Endian)...................................................................... 967
Figure 22.24 Target Bus Timeout Interrupt Generation Example 1
(Example in which the Target Device Asserts STOP at the Sixteenth Clock Cycle
after FRAME Was Asserted).................................................................................. 978
Figure 22.25 Target Bus Timeout Interrupt Generation Example 2 (Example in which
the Target Device Takes 8 Clock Cycles to Prepare for the Third Data Transfer). 979
Figure 22.26 Master Bus Timeout Interrupt Generation Example 1 (Example in which
the Master Device Prepares the Data and Asserts IRDY at the Eighth Clock
Cycle after FRAME Was Asserted) ....................................................................... 979
Figure 22.27 Master Bus Timeout Interrupt Generation Example 2 (Example in which
the Master Device Takes 8 Clock Cycles to Prepare for the Third Data
Transfer following the Second Data Phase) ........................................................... 980
Section 23 Electrical Characteristics
Figure 23.1 EXTAL Clock Input Timing ..............................................................................
Figure 23.2 (1) CKIO Clock Output Timing ........................................................................
Figure 23.2 (2) CKIO Clock Output Timing ........................................................................
Figure 23.3 Power-On Oscillation Settling Time ..................................................................
Figure 23.4 Standby Return Oscillation Settling Time (Return by RESET or MRESET) ....
Figure 23.5 Power-On Oscillation Settling Time ..................................................................
Figure 23.6 Standby Return Oscillation Settling Time (Return by RESET or MRESET) ....
Figure 23.7 Standby Return Oscillation Settling Time (Return by NMI)..............................
Figure 23.8 Standby Return Oscillation Settling Time (Return by IRL3–IRL0)...................
Figure 23.9 PLL Synchronization Settling Time in Case of RESET, MRESET or
NMI Interrupt .....................................................................................................
Figure 23.10 PLL Synchronization Settling Time in Case of IRL Interrupt............................
Figure 23.11 Control Signal Timing........................................................................................
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