SH7751 Datasheet, PDF (75/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figures
Section 1 Overview
Figure 1.1 Block Diagram of SH7751/SH7751R Group Functions......................................... 9
Figure 1.2 Pin Arrangement (256-Pin QFP) ............................................................................ 10
Figure 1.3 Pin Arrangement (256-Pin BGA)........................................................................... 11
Figure 1.4 Pin Arrangement (292-Pin BGA)........................................................................... 12
Section 2 Programming Model
Figure 2.1 Data Formats .......................................................................................................... 47
Figure 2.2 CPU Register Configuration in Each Processor Mode........................................... 50
Figure 2.3 General Registers ................................................................................................... 52
Figure 2.4 Floating-Point Registers ......................................................................................... 54
Figure 2.5 Data Formats In Memory ....................................................................................... 60
Figure 2.6 Processor State Transitions .................................................................................... 61
Section 3 Memory Management Unit (MMU)
Figure 3.1 Role of the MMU ................................................................................................... 65
Figure 3.2 MMU-Related Registers......................................................................................... 67
Figure 3.3 Physical Address Space (MMUCR.AT = 0) .......................................................... 71
Figure 3.4 P4 Area................................................................................................................... 72
Figure 3.5 External Memory Space ......................................................................................... 74
Figure 3.6 Virtual Address Space (MMUCR.AT = 1)............................................................. 75
Figure 3.7 UTLB Configuration .............................................................................................. 78
Figure 3.8 Relationship between Page Size and Address Format............................................ 79
Figure 3.9 ITLB Configuration................................................................................................ 82
Figure 3.10 Flowchart of Memory Access Using UTLB........................................................... 83
Figure 3.11 Flowchart of Memory Access Using ITLB ............................................................ 84
Figure 3.12 Operation of LDTLB Instruction............................................................................ 86
Figure 3.13 Memory-Mapped ITLB Address Array.................................................................. 95
Figure 3.14 Memory-Mapped ITLB Data Array 1 .................................................................... 96
Figure 3.15 Memory-Mapped ITLB Data Array 2 .................................................................... 97
Figure 3.16 Memory-Mapped UTLB Address Array ................................................................ 98
Figure 3.17 Memory-Mapped UTLB Data Array 1................................................................... 99
Figure 3.18 Memory-Mapped UTLB Data Array 2................................................................... 100
Section 4 Caches
Figure 4.1 Cache and Store Queue Control Registers (CCR).................................................. 103
Figure 4.2 Configuration of Operand Cache (SH7751) ........................................................... 106
Figure 4.3 Configuration of Operand Cache (SH7751R) ........................................................ 107
Rev.4.00 Oct. 10, 2008 Page lxxv of xcviii
REJ09B0370-0400