SH7751 Datasheet, PDF (996/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
Bits 31 to 0—Address Log (ALOG31 to 0): PIC address data (value of A/D line) at time of error.
(Initial value is undefined.)
22.2.23 PCI Command Data Register at Error (PCICLR)
Bit: 31
30
29
28
27
26
25
24
MSTPIO MSTDMA0 MSTDMA1 MSTDMA2 MSTDMA3 TGT
—
—
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
— CMDLOG3 CMDLOG2 CMDLOG1 CMDLOG0
Initial value:
0
0
0
0
—
—
—
—
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
The PCI command data register at error (PCICLR) stores the type of transfer (MSTPIO,
MSTDMA0, MSTDMA1, MSTDMA2, MSTDMA3, or TGT) when an error occurs on the PCI
bus, and the PCI command (CMDLOG [3:0]). It is a 32-bit register that can be read from both the
PP bus and PCI bus.
Although bits 31 to 26 of the PCICLR register are initialized at a power-on reset and a software
reset, bits 3 through 0 are not initialized. When an error is detected, 1 is set in one of bits 31 to 26,
and the relevant command value is retained in bits 3 to 0.
Rev.4.00 Oct. 10, 2008 Page 898 of 1122
REJ09B0370-0400