SH7751 Datasheet, PDF (517/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
CKIO
Address
Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce Tpc
Row
c1
c2
c8
CSn
RD/WR
RAS
CASn
D31–D0
(read)
d1
d2
d8
BS
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.18 Burst Access Timing in DRAM EDO Mode
RAS Down Mode: This LSI has an address comparator for detecting row address matches in burst
mode. By using this address comparator, and also setting RAS down mode specification bit RASD
to 1, it is possible to select RAS down mode, in which RAS remains asserted after the end of an
access. When RAS down mode is used, if the refresh cycle is longer than the maximum DRAM
RAS assert time, the refresh cycle must be decreased to or below the maximum value of t_RAS.
In RAS down mode, in the event of an access to an address with a different row address, an access
to a different area, a refresh request, or a bus release request, RAS is negated and the necessary
operation is performed. When DRAM access is resumed after this, since this is the start of RAS
down mode, the operation starts with row address output. Timing charts are shown in figures
13.19 (1), (2), (3), and (4).
Rev.4.00 Oct. 10, 2008 Page 419 of 1122
REJ09B0370-0400