SH7751 Datasheet, PDF (328/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Pipelining
Functional
Category No. Instruction
Data transfer 32 MOV.W
instructions _{33 MOV.L}
R0,@(disp,Rn)
Rm,@(disp,Rn)
34 MOV.B Rm,@(R0,Rn)
35 MOV.W Rm,@(R0,Rn)
36 MOV.L Rm,@(R0,Rn)
37 MOV.B R0,@(disp,GBR)
38 MOV.W R0,@(disp,GBR)
39 MOV.L R0,@(disp,GBR)
40 MOVCA.L R0,@Rn
41 MOVT Rn
42 OCBI
@Rn
43 OCBP @Rn
44 OCBWB @Rn
45 PREF
@Rn
46 SWAP.B Rm,Rn
47 SWAP.W Rm,Rn
48 XTRCT Rm,Rn
Fixed-point 49
arithmetic
instructions
50
51
ADD
ADD
ADDC
Rm,Rn
#imm,Rn
Rm,Rn
52 ADDV
Rm,Rn
53 CMP/EQ #imm,R0
54 CMP/EQ Rm,Rn
55 CMP/GE Rm,Rn
56 CMP/GT Rm,Rn
57 CMP/HI Rm,Rn
58 CMP/HS Rm,Rn
59 CMP/PL Rn
60 CMP/PZ Rn
61 CMP/STR Rm,Rn
62 DIV0S Rm,Rn
Instruc-
Execu-
Lock
tion Issue
tion
Group Rate Latency Pattern Stage Start Cycles
LS
1
1
#2
— ——
LS
1
1
#2
— ——
LS
1
1
#2
— ——
LS
1
1
#2
— ——
LS
1
1
#2
— ——
LS
1
1
#3
— ——
LS
1
1
#3
— ——
LS
1
1
#3
— ——
LS
1
3–7
#12
MA 4
3–7
EX
1
1
#1
— ——
LS
1
1–2
#10
MA 4
1–2
LS
1
1–5
#11
MA 4
1–5
LS
1
1–5
#11
MA 4
1–5
LS
1
1
#2
— ——
EX
1
1
#1
— ——
EX
1
1
#1
— ——
EX
1
1
#1
— ——
EX
1
1
#1
— ——
EX
1
1
#1
— ——
EX
1
1
#1
— ——
EX
1
1
#1
— ——
MT
1
1
#1
— ——
MT
1
1
#1
— ——
MT
1
1
#1
— ——
MT
1
1
#1
— ——
MT
1
1
#1
— ——
MT
1
1
#1
— ——
MT
1
1
#1
— ——
MT
1
1
#1
— ——
MT
1
1
#1
— ——
EX
1
1
#1
— ——
Rev.4.00 Oct. 10, 2008 Page 230 of 1122
REJ09B0370-0400