SH7751 Datasheet, PDF (533/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Single Write: The basic timing chart for write access is shown in figure 13.27. In a single write
operation, following the Tr cycle in which ACTV command output is performed, a WRITA
command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data
is output at the same time as the write command. In the case of a write with auto-precharge,
precharging of the relevant bank is performed in the synchronous DRAM after completion of the
write command, and therefore no command can be issued for the synchronous DRAM until
precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a
read access, cycle Trwl is also added as a wait interval until precharging is started following the
write command. Issuance of a new command for the same bank is postponed during this interval.
The number of Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. DACK is asserted
two cycles before the data write cycle.
This LSI supports burst-length 4 burst read and burst write operations of synchronous DRAM. A
wait cycle is therefore generated even with single write operations.
Rev.4.00 Oct. 10, 2008 Page 435 of 1122
REJ09B0370-0400