SH7751 Datasheet, PDF (40/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page Revision (See Manual for Details)
22.2.24 PCI Arbiter 901
Interrupt Register
(PCIAINT)
Description amended of Bit 0
Bit 0—Read Data Parity Error Interrupt (DPERR_RD): Indicates
the detection of the assertion of PERR in a data read operation
when a device other than the PCIC is operating as the bus
master.
22.2.25 PCI Arbiter 902
Interrupt Mask Register
(PCIAINTM)
Description amended
The PCI arbiter interrupt mask register (PCIAINTM) sets
interrupt masks for the individual interrupts that occur due to
errors generated during PCI transfers performed by other PCI
devices when the PCIC is operating as the host with the
arbitration function. It is a 32-bit register that is readable and
writable from both the peripheral bus and the PCI bus. Each bit
is set to 0 to disable the respective interrupt, or 1 to enable that
interrupt.
22.2.29 PCI DMA
907, 908 Description amended
Transfer Local Bus Start
Address Register [3:0]
(PCIDLA [3:0])
The transfer address of a byte boundary or character boundary
can be set, but the 2 least significant bits of the register are
ignored, and the data of the longword boundary is transferred.
Note that the local bus starting address set in this register is the
external address of the SH bus.
…
Bits 28 to 0—DMA Transfer Local Bus Starting Address
(PDLA28 to 0): These bits set the starting address of the local
bus (external address of SH bus) for DMA transfer. Bits 28 to
26 indicate the local bus area.
22.2.30 PCI DMA
909
Transfer Counter
Register [3:0] (PCIDTC
[3:0])
Description amended
Bits 25 to 0—DMA Transfer Byte Count (PTC25 to 0): Specify
the number of bytes in DMA transfer. The maximum number of
transfer bits are 64 MB (when set to H'00000000).
22.2.31 PCIDMA
910
Description amended
Control Register
[3:0](PCIDCR[3:0])
When setting the DMASTOP bit, do not write 1 to the
DMASTART bit. Also, write the same setting at the start of
transfer to the DMAIM, DMAIS, LAHOLD, IOSEL and DIR bits.
22.2.36 PCI Power 920
Management Interrupt
Mask Register
(PCIPINTM)
Description amended
Bit 1—Power State D3 (DPERR_WT): Transition request to
power-down mode interrupt mask for this LSI.
Bit 0—Power State D0 (DPERR_RD): Restore from power-
down mode interrupt mask for this LSI.
Rev.4.00 Oct. 10, 2008 Page xl of xcviii
REJ09B0370-0400