SH7751 Datasheet, PDF (1038/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
Note: * In version 2.1 of the PCI specifications the I/O space for PCI devices is defined as
being no more than 256 bytes. As a result, when the SH7751 is used in a PCI non-host
device, for example on an add-in card, it may be identified as an unusable device
during device configuration because it requires an I/O space larger than 256 bytes.
Configuration-Read and Configuration-Write Commands: When the PCIC operates as a non-
host device, the configuration registers of the PCIC are accessed by using configuration-read and
configuration-write commands.
Configuration access only supports single transfers. In the SH7751, the values of the byte-enable
signals (BE [3:0]) are ignored, and longword accesses are carried out inside the PCIC*. In the
SH7751R, the values of BE[3:0] are enabled. When executing a configuration-write operation,
specify B'0000 as the BE [3:0] value.
Note: * Version 2.1 of the PCI specifications specifies that any combination of byte-enable
signal (BE[3:0]) values must be allowed when accepting a configuration access. As a
result, when byte or word access is specified by the combination of BE[3:0], the
remaining portion of the data in the longword unit is also overwritten by the write
operation.
Locked Transfer: Locked transfers are supported, but the locked space becomes the whole
memory of the PCIC in the case of memory transfers, and becomes the whole register space in the
case of I/O transfers or configuration transfers. While the memory is locked, retry is returned for
all memory accesses of the PCIC from other PCI devices. Register access is, however, accepted.
Similarly, while the registers are locked, retry is returned for all I/O accesses or configuration
accesses of the PCIC from another PCI device, but memory access is accepted.
22.3.9 DMA Transfers
DMA transfers allow the high-speed transfer of data between devices connected to the local bus
and PCI bus when the PCIC has bus privileges as master. The following commands are supported
in the case of DMA transfers:
• Memory read, memory write, I/O read, and I/O write
(Locked transfers are not supported.)
(High-speed back-to-back transfers are not supported.)
There are four DMA channels. In each channel, a maximum of 64MB can be set for each transfer,
the number of transfer bytes and the starting address for the transfer being set at a longword
boundary.
Rev.4.00 Oct. 10, 2008 Page 940 of 1122
REJ09B0370-0400