SH7751 Datasheet, PDF (1020/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
• The PCIC-BSC performs the same operations as the slave mode of the BSC. Therefore, the
MATER bit of the PCI bus control register 1 (PCIBCR1) shows the slave status.
• Because the PCIC-BSC operates in slave mode, the bus privilege is handed to the BSC once
per bus cycle.
• The external memory capable of data transfers to the PCI bus is SRAM, DRAM, synchronous
DRAM, and MPX*².
• The memory data width is 32-bit or 16-bit only (only 32-bit in the case of synchronous
DRAM).
• Do not specify other external memory types (burst ROM, MPX, byte control SRAM or
PCMCIA) as the external memory for data transfers with the PCI bus.
• Because the PCIC-BSC operates in slave mode, the RAS-down mode of DRAM and SDRAM
is not available.
• The local bus supports both big and little endian. However, the PCI bus supports only little
endian.
The PCI-BSC does not support mode register setting of synchronous DRAM nor refreshing of
synchronous DRAM or DRAM. These must be executed by the BSC.
Also, do not implement any settings that are not allowed in slave mode in the PCIC-BSC registers.
This is because bit 30: master/slave flag (MASTER) of the PCIBCR1 is fixed Low, regardless of
the value of the external master/slave setting pin (MD7) at a power-on reset, and the PCIC-BSC
therefore is set in slave mode.
In the case of external memory not used for data transfers with the PCI bus, make the same
settings as the corresponding bus state controller register.
These registers are initialized at a power-on reset, but not by a software reset.
Notes: 1. This register is provided only in the SH7751R, not provided in the SH7751.
2. MPX is supported only in the SH7751R, not supported in the SH7751.
Rev.4.00 Oct. 10, 2008 Page 922 of 1122
REJ09B0370-0400