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SH7751 Datasheet, PDF (179/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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3. Memory Management Unit (MMU)
⢠C: Cacheability bit
Indicates whether a page is cacheable.
0: Not cacheable
1: Cacheable
When control register space is mapped, this bit must be cleared to 0.
When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0
or set the WT bit to 1.
⢠D: Dirty bit
Indicates whether a write has been performed to a page.
0: Write has not been performed
1: Write has been performed
⢠WT: Write-through bit
Specifies the cache write mode.
0: Copy-back mode
1: Write-through mode
When performing PCMCIA space mapping in the cache enabled state, either set this bit to 1 or
clear the C bit to 0.
⢠SA: Space attribute bits
Valid only when the page is mapped onto PCMCIA connected to area 5 or 6.
000: Undefined
001: Variable-size I/O space (base size according to IOIS16 signal)
010: 8-bit I/O space
011: 16-bit I/O space
100: 8-bit common memory space
101: 16-bit common memory space
110: 8-bit attribute memory space
111: 16-bit attribute memory space
⢠TC: Timing control bit
Used to select wait control register bits in the bus control unit for areas 5 and 6.
0: WCR2 (A5W2âA5W0) and PCR (A5PCW1âA5PCW0, A5TED2âA5TED0, A5TEH2â
A5TEH0) are used
1: WCR2 (A6W2âA6W0) and PCR (A6PCW1âA6PCW0, A6TED2âA6TED0, A6TEH2â
A6TEH0) are used
Rev.4.00 Oct. 10, 2008 Page 81 of 1122
REJ09B0370-0400
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