SH7751 Datasheet, PDF (485/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
A2 of this LSI, and A1 of the synchronous DRAM is connected to A3 of this LSI, the value
actually written to the synchronous DRAM is the value of “X” shifted 2 bits to the right.
For example, to write H'0230 to the area 2 SDMR register, arbitrary data is written to address
H'FF900000 (address “Y”) + H'08C0 (value “X”) (= H'FF9008C0). As a result, H'0230 is written
to the SDMR register. The range of value “X” is H'0000 to H'0FFC.
Similarly, to write H'0230 to the area 3 SDMR register, arbitrary data is written to address
H'FF940000 (address “Y”) + H'08C0 (value “X”) (= H'FF9408C0). As a result, H'0230 is written
to the SDMR register. The range of value “X” is H'0000 to H'0FFC.
The lower 16 bits of the address are set in the synchronous DRAM mode register.
The burst length is 4 and 8*. Setting to SDMR writes into the following addresses in byte size.
Bus Width
32
32
Burst length
4
8*
CAS Latency
1
2
3
1
2
3
Area 2
H'FF900048
H'FF900088
H'FF9000C8
H'FF90004C
H'FF90008C
H'FF9000CC
Area 3
H'FF940048
H'FF940088
H'FF9400C8
H'FF94004C
H'FF94008C
H'FF9400CC
Note: * SH7751R only
For a 32-bit bus:
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address 0 0 0 0 0 0 0 0 0 LMO LMO LMO WT BL2 BL1 BL0
DE2 DE1 DE0
←⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯→
10 bits set in case of 32-bit bus width
LMODE: CAS latency
BL:
Burst length
WT:
Wrap type (0: Sequential)
Rev.4.00 Oct. 10, 2008 Page 387 of 1122
REJ09B0370-0400