SH7751 Datasheet, PDF (1032/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
When using the CKIO clock, please note the limitations on CKIO clock frequency, stability, and
load capacitance that can be connected to the CKIO pin. Check the clock oscillation circuit and
electrical characteristics in section 10, Clock Oscillation Circuits, and section 23, Electrical
Characteristics.
22.3.6 PCI Bus Arbitration in Non-host Mode
When operating in non-host mode, the PCI bus arbitration function in the PCIC is disabled and
PCI bus arbitration is performed according to the specifications of the externally connected PCI
bus arbiter.
In this case, the PCIC must request PCI bus privileges from the PCI bus arbiter (system host
device). The PCIGNT1/REQOUT pins are used for the bus request signals, and the
PCIREQ1/GNTIN pins are used for the bus grant signals. When the bus grant signals are asserted
when the bus request signals are not asserted, the PCIC performs bus parking.
Also, when the PCIC is used as a target device that does not request bus privileges, the
PCIREQ1/GNTIN pins must be fixed at the high level.
22.3.7 PIO Transfers
PIO transfer is a data transfer mode in which a peripheral bus is used to access the memory space
and I/O space of the PCI bus.
The following commands are supported in PIO transfer mode:
• Memory read, memory write, I/O read, and I/O write
• Locked transfer (High-speed back-to-back transfers are not supported.)
In PIO transfer mode, only single transfers are supported. 32-byte burst transfers are not
supported.
In memory transfers and I/O transfers, the supported, so generate byte enable signals (BE[3:0]) to
match the respective access sizes and output these signals to the PCI bus. Access sizes are byte,
word, and longword.
Locked transfers are supported only in the case of memory transfers and I/O transfers. High-speed
back-to-back transfers are not supported.
Rev.4.00 Oct. 10, 2008 Page 934 of 1122
REJ09B0370-0400