SH7751 Datasheet, PDF (25/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page Revision (See Manual for Details)
13.3.5 Synchronous
DRAM Interface
427, 428 Description deleted
The control signals for connection of synchronous DRAM are
RAS, CASS, RD/WR, CS2 or CS3, DQM0 to DQM3, and CKE.
…
Commands for synchronous DRAM are specified by RAS,
CASS, RD/WR, and specific address signals. …
Figure 13.23 Example 428
of 32-Bit Data Width
Synchronous DRAM
Connection (Area 3)
Figure amended
SH7751/SH7751R
A11–A2
CKIO
CKE
CS3
RAS
CASS
RD/WR
D31–D16
DQM3
DQM2
Burst Read:
431
Figure 13.24 Basic
Timing for Synchronous
DRAM Burst Read
Figure amended
Refreshing:
448
• Auto-Refreshing
Figure 13.36
Synchronous DRAM
Auto-Refresh Timing
• Self-Refreshing
450
Figure 13.37
Synchronous DRAM
Self-Refresh Timing
Power-On Sequence: 452
Figure 13.38 (1)
Synchronous DRAM
Mode Write Timing
(PALL)
Figure amended
D31−D0
Figure amended
D31−D0
Figure amended
D31–D0
Rev.4.00 Oct. 10, 2008 Page xxv of xcviii
REJ09B0370-0400