SH7751 Datasheet, PDF (1213/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

G. Power-On and Power-Off Procedures
Appendix G Power-On and Power-Off Procedures
G.1 Power-On Stipulations
1. Supply power to power supply V_DDQ and to I/O, RTC, CPG, PLL1, and PLL2 simultaneously.
2. Perform input to the signal lines (RESET, MRESET, MD0 to MD10, external clock, etc.) after
or at the same time power is supplied to V_DDQ. Applying input to signal lines before power is
supplied to V_DDQ could damage the product.
⎯ Drive the RESET signal low when power is first supplied to V_DDQ.
3. Apply power such that the voltage of power supply V_DD is less than 1.2 V until the voltage of
power supply V_DDQ reaches 2 V. Note that the on-chip PLL circuit (PLL2) may not operate
correctly if this condition is not met.
4. It is recommended to apply power first to power supply V_DDQ and then to power supply V_DD.
5. In addition to 1., 2., 3., and 4. above, also observe the stipulations in G.3. Furthermore:
⎯ There are no time restrictions on the power-on sequence for power supply V_DDQ and power
supply V_DD with regard to the LSI alone. Refer to figure G.1. Nevertheless, it is
recommended that the power-on sequence be completed in as short a time as possible.
⎯ When the LSI is mounted on a board and connected to other elements, ensure that –0.3 V <
Vin < V_DDQ + 0.3 V. In addition, the time limit for the rise of either power supply V_DDQ or
power supply V_DD from V_DDQ ≥ 1.0 V or V_DD ≥ 0.5 V, respectively, to above the minimum
values in the LSI’s guaranteed operation voltage range (V_DDQ (min.) and V_DD (min.)) is 100
ms (max.), as shown in figure G.2. The product may be damaged if this time limit is
exceeded. It is recommended that the power-on sequence be completed in as short a time as
possible.
G.2 Power-Off Stipulations
1. Power off power supply V_DDQ and I/O, RTC, CPG, PLL1, and PLL2 simultaneously.
2. There are no timing restrictions for the RESET and MRESET signal lines at power-off.
3. Cut off the input signal level for signal lines other than RESET and MRESET in the same
sequence as power supply V_DDQ.
4. It is recommended to first power off power supply V_DD and then power supply V_DDQ.
5. In addition to 1., 2., 3., and 4. above, also observe the stipulations in G.3. Furthermore:
⎯ There are no time restrictions on the power-off sequence for power supply V_DDQ and power
supply V_DD with regard to the LSI alone. Refer to figure G.2. Nevertheless, it is
recommended that the power-off sequence be completed in as short a time as possible.
Rev.4.00 Oct. 10, 2008 Page 1115 of 1122
REJ09B0370-0400