SH7751 Datasheet, PDF (436/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
13.1.3 Pin Configuration
Table 13.1 shows the BSC pin configuration.
Table 13.1 BSC Pins
Name
Signals
I/O
Address bus
A25–A0
O
Data bus
D31–D0
I/O
Bus cycle start BS
O
Chip select 6–0 CS6–CS0
O
Read/write
RD/WR
O
Row address
RAS
O
strobe
Read/column
RD/CASS/
O
address strobe/ FRAME
cycle frame
Data enable 0
WE0/REG
O
Data enable 1
WE1
O
Data enable 2
WE2/ICIORD O
Data enable 3
WE3/ICIOWR O
Description
Address output
Data input/output
Signal that indicates the start of a bus cycle
When setting synchronous DRAM interface or MPX
interface: asserted once for a burst transfer
For other burst transfers: asserted each data cycle
Chip select signals that indicate the area being
accessed
CS5 and CS6 are also used as PCMCIA CE1A and
CE1B
Data bus input/output direction designation signal
Also used as the DRAM/synchronous
DRAM/PCMCIA interface write designation signal
RAS signal when setting DRAM/synchronous DRAM
interface
Strobe signal that indicates a read cycle
When setting synchronous DRAM interface: CAS
signal
When setting MPX interface: FRAME signal
When setting PCMCIA interface: REG signal
When setting SRAM interface: write strobe signal for
D7–D0
When setting PCMCIA interface: write strobe signal
When setting SRAM interface: write strobe signal for
D15–D8
When setting PCMCIA interface: ICIORD signal
When setting SRAM interface: write strobe signal for
D23–D16
When setting PCMCIA interface: ICIOWR signal
When setting SRAM interface: write strobe signal for
D31–D24
Rev.4.00 Oct. 10, 2008 Page 338 of 1122
REJ09B0370-0400