SH7751 Datasheet, PDF (43/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
22.3.11 PCI Bus Basic 947
Interface
Target Read/Write Cycle 952
Timing:
22.4.4 Endian Control 963
in Target Transfers
(Memory Read/Memory
Write)
22.6.1 Interrupts from 970
PCIC to CPU
Power Management
Interrupt (Transition
Request to Normal
Status) (PCIPWON):
Power Management
Interrupt (Transition
Request to Power-Down
Mode) (PCIPWDWN):
Revision (See Manual for Details)
Description amended
The PCI interface of the MCU supports a subset of version 2.1
of the PCI specifications and enables connection to a device
with a PCI bus interface.
Description amended and note added
The following restrictions apply to the SH7751. With the
SH7751R, in the following case the values of data are
discarded for a target read that is executed immediately after a
target write because the data read in an earlier read operation
that was carried out by a different PCI device are discarded.
[Restrictions]
In a system in which access is made to the same address*¹ in
local memory by two or more PCI devices, the data cannot be
guaranteed when a target read is performed immediately after a
target write.
…
Notes: 1. Address matching AD[31:2] in the address phase.
2. The address that does not correspond to the
address AD[31:2] on a longword boundary.
Description amended
As shown in table 22.12, the byte data boundary mode is used,
for all transfers.
Description amended
Power Management Interrupt (Transition Request to Normal
Status) (PCIPWON): The power state D0 (PWRST_D0) bit of
the PCI power management interrupt register (PCIPINT) is set.
The power state D0 interrupt mask can be set using the power
state D0 (PWRST_D0) bit of the PCI power management
interrupt mask register (PCIPINTM).
Description amended
Power Management Interrupt (Transition Request to Power-
Down Mode) (PCIPWDWN): The power state D3 (PWRST_D3)
bit of the PCI power management interrupt register (PCIPINT)
is set. The power state D3 interrupt mask can be set using the
power state D3 (PWRST_D3) bit of the PCI power
management interrupt mask register (PCIPINTM).
Rev.4.00 Oct. 10, 2008 Page xliii of xcviii
REJ09B0370-0400