SH7751 Datasheet, PDF (365/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Clock Oscillation Circuits
Section 10 Clock Oscillation Circuits
10.1 Overview
The on-chip oscillation circuits comprise a clock pulse generator (CPG) and a watchdog timer
(WDT).
The CPG generates the clocks supplied inside the processor and performs power-down mode
control.
The WDT is a single-channel timer used to count the clock stabilization time when exiting standby
mode or the frequency is changed. It can be used as a normal watchdog timer or an interval timer.
10.1.1 Features
The CPG has the following features:
• Three clocks
The CPG can generate the CPU clock (Ick) used by the CPU, FPU, caches, and TLB, the
peripheral module clock (Pck) used by the peripheral modules, and the bus clock (Bck) used
by the external bus interface.
• Six clock modes
Any of six clock operating modes can be selected, with different combinations of CPU clock,
bus clock, and peripheral module clock division ratios after a power-on reset.
• Frequency change function
PLL (phase-locked loop) circuits and a frequency divider in the CPG enable the CPU clock,
bus clock, and peripheral module clock frequencies to be changed. Frequency changes are
performed by software in accordance with the settings in the frequency control register
(FRQCR).
• PLL on/off control
Power consumption can be reduced by stopping the PLL circuits during low-frequency
operation.
• Power-down mode control
It is possible to stop the clock in sleep mode and standby mode, and to stop specific modules
with the module standby function.
Rev.4.00 Oct. 10, 2008 Page 267 of 1122
REJ09B0370-0400