SH7751 Datasheet, PDF (41/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
22.2.38 PCIC-BSC
Registers
22.2.41 PIO Data
Register (PCIPDR)
22.3.3 PCIC
Initialization
Page
921
922
928
930
Revision (See Manual for Details)
Description added
The PCIC-BSC performs the same type of control as the slave
function of the bus controller (BSC). However, the PCIC-BSC
returns bus rights to the BSC after each data transfer of up to
32 bytes of data. There are six registers in the PCIC-BSC:
PCIBCR1 (equivalent to the BCR1 of the BSC), PCIBCR2
(equivalent to the BCR2 of the BSC), PCIBCR3 (equivalent to
the BCR3 of the BSC)*¹, PCIWCR1 (equivalent to the WCR1 of
the BSC), PCIWCR2 (equivalent to the WCR2 of the BSC),
PCIWCR3 (equivalent to the WCR3 of the BSC), and PCIMCR
(equivalent to the MCR of the BSC).
Description amended
• The external memory capable of data transfers to the PCI
bus is SRAM, DRAM, synchronous DRAM, and MPX*².
• Also, the memory data width is 32-bit or 16-bit only (only 32-
bit in the case of synchronous DRAM).
• Do not specify other external memory types (burst ROM,
MPX, byte control SRAM or PCMCIA) as the external
memory for data transfers with the PCI bus.
…
• Also, do not implement any settings that are not allowed in
slave mode in the PCIC-BSC registers. This is because bit
30: master/slave flag (MASTER) of the PCIBCR1 is fixed
Low, regardless of the value of the external master/slave
setting pin (MD7) at a power-on reset, and the PCIC-BSC
therefore is set in slave mode.
Description amended
Always write to this register before accessing the PCI
configuration space. Always read/write to this register after
setting the value in the PIO address register (PCIPAR).
Description amended
Also, as the BSC has BCR1.BREQEN bits that enable an
external request and a bus request from the PCIC to be
accepted, BCR1.BREQEN should be set to 1 when the PCIC is
used.
Rev.4.00 Oct. 10, 2008 Page xli of xcviii
REJ09B0370-0400