SH7751 Datasheet, PDF (42/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page Revision (See Manual for Details)
22.3.7 PIO Transfers 936
Figure amended
Figure 22.2 PIO
Memory Space Access
31 24 23
0
PCIMBR
Figure 22.3 PIO I/O 937
Space Access
Figure amended
31
PCIIOBR
LOCK identifier
18 17
0
22.3.8 Target
939
Transfers
I/O-Read and I/O-Write 940
Commands:
Configuration-Read and
Configuration-Write
Commands:
22.3.9 DMA Transfers 945
DMA Arbitration
LOCK identifier
Description amended
To make it possible to access two or more areas from the PCI
bus, set the address spaces so that multiple areas are covered.
…
Note amended
Note: * In version 2.1 of the PCI specifications the I/O
space for PCI devices is defined as being no more
than 256 bytes. As a result, when the SH7751 is
used in a PCI non-host device, for example on an
add-in card, it may be identified as an unusable
device during device configuration because it
requires an I/O space larger than 256 bytes.
Note amended
Note: * Version 2.1 of the PCI specifications specifies that
any combination of byte-enable signal (BE[3:0])
values must be allowed when accepting a
configuration access. As a result, when byte or word
access is specified by the combination of BE[3:0],
the remaining portion of the data in the longword
unit is also overwritten by the write operation.
Description amended
The arbitration circuit monitors the data transfer requests (data
write requests to the FIFO when the FIFO is empty and read
requests from the FIFO when it is full) 4 DMA transfer channels
to control the data transfers. For each transfer request, a
transfer of up to 32 bytes of data is performed.
Rev.4.00 Oct. 10, 2008 Page xlii of xcviii
REJ09B0370-0400