SH7751 Datasheet, PDF (991/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
When an error occurs, the bit corresponding to the error content is set to 1. Each interrupt
detection bit can be cleared to its initial status (0) by writing 1 to it. (Write clear)
Note that the error detection bits can be set even when the interrupt is masked.
The error source holding circuit can only store one error source. For this reason, any second or
subsequent error factors are not stored if errors occur consecutively.
Bits 31 to 16—Reserved: These bits always return 0 when read. Always write 0 to these bits.
Bit 15—Unlocked Transfer Detection Interrupt (M_LOCKON): When the PCIC is master, an
unlocked PIO transfer was performed when the I-specified target was locked.
Bit 14—Target Target Abort Interrupt (T_TGT_ABORT): Indicates the termination of
transaction by target abort when the PCIC is a target. Target abort is generated when the 2 least
significant address bits (bits 1, 0) and byte enable constitute an illegal combination (illegal byte
enable) during I/O transfer.
Bits 13 to 10—Reserved: These bits always return 0 when read. Always write 0 to these bits.
Bit 9—Target Memory Read Retry Timeout Interrupt (TGT_RETRY): When the PCIC is
target, the master did not attempt a retry within the prescribed number of PCI bus clocks (2¹⁵)
(detected only in the case of memory read operations).
Bit 8—Master Function Disable Error Interrupt (MST_DIS): Indicates that an attempt was
made to conduct a master operation (PIO transfer, DMA transfer) when bit 2 (BUM) of the
PCICONF1 was set to 0 to prohibit bus master operations.
Bit 7—Address Parity Error Detection Interrupt (ADRPERR): Address parity error detected.
Detects only when bit 6 (PER) and bit 8 (SER) of the PCICONF1 are both 1.
Bit 6—SERR Detection Interrupt (SERR_DET): When the PCIC is host, assertion of the SERR
signal was detected.
Bit 5—Target Write Data Parity Error Interrupt (T_DPERR_WT): When the PCIC is target,
a data parity error was detected while receiving a target write transfer (only detected when
PCICONFI bit 6 (PER) is 1).
Bit 4—Target Read PERR Detection Interrupt (T_PERR_DET): When the PCIC is target,
PERR was detected when receiving a target read transfer. Detects only when bit 6 (SER) of the
PCICONF1 is 1.
Rev.4.00 Oct. 10, 2008 Page 893 of 1122
REJ09B0370-0400