SH7751 Datasheet, PDF (1050/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
Target Read/Write Cycle Timing: The PCIC responds to target memory read accesses from an
external master by retries until 8 longword data are prepared in the PCIC's internal FIFO. That is,
it always responds to the first target read with a retry.
Also, if a target memory write access is made, the PCIC responds to all subsequent target memory
accesses with a retry until the write data is completely written to local memory. Thus, the content
of the data is guaranteed when data written to the target is immediately subject to a target read
operation.
The following restrictions apply to the SH7751. With the SH7751R, in the following case the
values of data are discarded for a target read that is executed immediately after a target write
because the data read in an earlier read operation that was carried out by a different PCI device are
discarded.
[Restrictions]
In a system in which access is made to the same address*¹ in local memory by two or more PCI
devices, the data cannot be guaranteed when a target read is performed immediately after a target
write.
The possibility of an error occurs when the target read immediately after the target write gets bus
privileges at the point the data is ready for a target read by a different PCI device prior to the target
write. In this case, the data prior to the target write is read. If such transfers are likely to occur,
implement either (a) or (b) below.
(a) If using the data that has been read, perform two read operations and use only the data from the
second read operation.
(b) If not using the data that has been read (if you are performing the read operation in order to
determine the timing for actually writing data to the destination), be sure that the read
address*² immediately after writing is different from the write address.
Notes: 1. Address matching AD[31:2] in the address phase.
2. The address that does not correspond to the address AD[31:2] on a longword boundary.
Only single transfers are supported in the case of target accesses of the configuration space and
I/O space. If there is a burst access request, the external master is disconnected on completion of
the first transfer.
Note that the DEVSEL response speed is fixed at 2 clocks (Medium) in the case of target access of
the PCIC.
Rev.4.00 Oct. 10, 2008 Page 952 of 1122
REJ09B0370-0400