SH7751 Datasheet, PDF (438/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Notes: 1. MD3/CE2A input/output switching is performed by BCR1.A56PCM. Output is selected
when BCR1.A56PCM = 1.
2. MD4/CE2B input/output switching is performed by BCR1.A56PCM. Output is selected
when BCR1.A56PCM = 1.
13.1.4 Register Configuration
The BSC has the 11 registers shown in table 13.2. In addition, the synchronous DRAM mode
register incorporated in synchronous DRAM can also be accessed as this LSI register. The
functions of these registers include control of interfaces to various types of memory, wait states,
and refreshing.
Table 13.2 BSC Registers
Name
Abbrevia- R/W Initial
tion
Value
P4
Address
Area 7
Address
Access
Size
Bus control register 1 BCR1
R/W H'0000 0000 H'FF80 0000 H'1F80 0000 32
Bus control register 2
Bus control register 3*²
Bus control register 4*²
BCR2
BCR3
BCR4
R/W H'3FFC
H'FF80 0004 H'1F80 0004 16
R/W H'0001
H'FF80 0050 H'1F80 0050 16
R/W H'0000 0000 H'FE0A 00F0 H'1E0A 00F0 32
Wait state control
register 1
WCR1
R/W H'7777 7777 H'FF80 0008 H'1F80 0008 32
Wait state control
register 2
WCR2
R/W H'FFFE EFFF H'FF80 000C H'1F80 000C 32
Wait state control
register 3
WCR3
R/W H'0777 7777 H'FF80 0010 H'1F80 0010 32
Memory control register MCR
R/W H'0000 0000 H'FF80 0014 H'1F80 0014 32
PCMCIA control register PCR
R/W H'0000
H'FF80 0018 H'1F80 0018 16
Refresh timer
control/status register
RTCSR
R/W H'0000
H'FF80 001C H'1F80 001C 16
Refresh timer counter RTCNT R/W H'0000
H'FF80 0020 H'1F80 0020 16
Refresh time constant RTCOR R/W H'0000
counter
H'FF80 0024 H'1F80 0024 16
Refresh count register
Synchronous
DRAM mode
registers
For
area 2
For
area 3
RFCR
SDMR2
SDMR3
R/W H'0000
W—
H'FF80 0028 H'1F80 0028 16
H'FF90 xxxx*¹ H'1F90 xxxx 8
H'FF94 xxxx*¹ H'1F94 xxxx
Notes: 1. For details, see section 13.2.10, Synchronous DRAM Mode Register (SDMR).
2. SH7751R only
Rev.4.00 Oct. 10, 2008 Page 340 of 1122
REJ09B0370-0400