SH7751 Datasheet, PDF (173/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Memory Management Unit (MMU)
3.3.3 Virtual Address Space
Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical address space in
the SH-4 to be mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte, page
units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be
increased to a maximum of 256. This is called the virtual address space. Mapping from virtual
address space to 29-bit external memory space is carried out using the TLB. Only when area 7 in
external memory space is accessed using virtual address space, addresses H'1C00 0000 to H'1FFF
FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4 area control
register area in the physical address space. Virtual address space is illustrated in figure 3.6.
256
P0 area
Cacheable
Address translation possible
External 256
memory space
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
U0 area
Cacheable
Address translation possible
P1 area
Cacheable
Address translation not possible
P2 area
Non-cacheable
Address translation not possible
P3 area
Cacheable
Address translation possible
P4 area
Non-cacheable
Address translation not possible
Privileged mode
Address error
Store queue area
Address error
User mode
Figure 3.6 Virtual Address Space (MMUCR.AT = 1)
In the state of cache enabling, when the areas of P0, P3, and U0 are mapped onto the area of the
PCMCIA interface by means of the TLB, it is necessary either to specify 1 for the WT bit or to
specify 0 for the C bit on that page. At that time, the regions are accessed by the values of SA and
TC set in page units of the TLB.
Rev.4.00 Oct. 10, 2008 Page 75 of 1122
REJ09B0370-0400