SH7751 Datasheet, PDF (197/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Memory Management Unit (MMU)
1. UTLB data array 1 read
PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry
corresponding to the entry set in the address field.
2. UTLB data array 1 write
PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry
corresponding to the entry set in the address field.
31
24 23
Address field _{1 1 1 1 0 1 1 1 0}
14 13
87
0
E
31 30 29 28
Data field
PPN
10 9 8 7 6 5 4 3 2 1 0
V PR C D
Legend:
PPN: Physical page number
V: Validity bit
E: Entry
SZ: Page size bits
D: Dirty bit
PR: Protection key data
SZ SH WT
C: Cacheability bit
SH: Share status bit
WT: Write-through bit
: Reserved bits (0 write value, undefined read value)
Figure 3.17 Memory-Mapped UTLB Data Array 1
3.7.6 UTLB Data Array 2
UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and SA and TC to be written to data array 2 are specified in the data
field.
In the address field, bits [31:23] have the value H'F78 indicating UTLB data array 2, and the entry
is selected by bits [13:8].
In the data field, TC is indicated by bit [3], and SA by bits [2:0].
The following two kinds of operation can be used on UTLB data array 2:
1. UTLB data array 2 read
SA and TC are read into the data field from the UTLB entry corresponding to the entry set in
the address field.
Rev.4.00 Oct. 10, 2008 Page 99 of 1122
REJ09B0370-0400