SH7751 Datasheet, PDF (594/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
• When a BREQ signal is input from the external device while DRAM/synchronous DRAM is
set to CAS-before-RAS refresh and auto-refresh in master mode (MD7 = 1), assertion of the
BACK signal (low-level) in response to the BREQ signal may be for only one cycle at CKIO.
Both above phenomena can be avoided by not using the BREQ signal. If the BREQ signal is to be
used, disable refresh operations during normal operation. If refresh operations are required, carry
them out at one time with the BREQEN bit in BCR1 cleared to 0.
Synchronous DRAM Mode Register Settings (SH7751 Only): The following conditions must
be satisfied when setting the synchronous DRAM mode register.
• The DMAC must not be activated until synchronous DRAM mode register setting is
completed.*¹
• Register setting for the on-chip peripheral modules*² must not be performed until synchronous
DRAM mode register setting is completed.*³
Notes: 1. If a conflict occurs between synchronous DRAM mode register setting and memory
access using the DMAC, neither operation can be guaranteed.
2. This applies to the following on-chip peripheral modules: CPG, RTC, INTC, TMU,
SCI, SCIF, and H-UDI.
3. If synchronous DRAM mode register setting is performed immediately following write
access to the on-chip peripheral modules*², the values written to the on-chip peripheral
modules cannot be guaranteed. Note that following power-on, synchronous DRAM
mode register settings should be performed before accessing synchronous DRAM.
After making mode register settings, do not change them.
Rev.4.00 Oct. 10, 2008 Page 496 of 1122
REJ09B0370-0400