SH7751 Datasheet, PDF (948/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
No. Pin Name
PCI
Standard
Signal
Name Function
I/O Status
in Operating Modes
I/O Pull-up
Host
Non-host
Type Resistor*¹ Master Target Master Target Remarks
17 PCIREQ2/ REQ2 Bus request
t/s
Yes
I
I
—
—
MD9
(host function)
PCI clock switch in
(BCLK/PCICLK)
I
I
I
I
*²
18 PCIREQ3/ REQ3 Bus request (host t/s
Yes
I
I
—
—
MD10
function)
Host bridge
in
function ON/OFF
I
I
I
I
*²
19 PCIREQ4 REQ4 Bus request
t/s
Yes
I
I
—
—
(host function)
20 PCIGNT4 GNT4 to Bus grant
t/s
to
GNT2 (host function)
PCIGNT2
O
O
—
—
21 IDSEL
IDSEL Config device
in
select
—
—
I
I
*³
Legend:
in: Input
out: Output
s/t/s: Sustained try state
o/d: Open drain
t/s: Try state
Notes: 1. Terminal provided with a pull-up resistor.
2. The values of external pins are sampled in a power-on reset by means of the RESET
pin.
3. Pull down this pin to low level when IDSEL is not in use. If a configuration access to an
external PCI device occurs while IDSEL is high level, the PCIC itself may respond.
22.1.4 Register Configuration
The PCIC has the PCI configuration registers and PCI control registers shown in table 22.2, 22.3
and 22.4. Also, the PCI bus address space is allocated to the internal bus for the peripheral
modules, making it possible to access the PCI bus by program IO (PIO). Not only do these
registers control the PCI bus but also enable high-speed data transfers between the PCI device and
memory on the SH-4 external data bus (hereinafter, the SH-4 external data bus is referred to as the
local bus to distinguish it from the PCI bus).
Rev.4.00 Oct. 10, 2008 Page 850 of 1122
REJ09B0370-0400