SH7751 Datasheet, PDF (976/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
Bits 31 to 24—Designation of Maximum Latency (MLAT7 to 0): These bits specify the
maximum time from the time the PCI master device demands bus privileges and to the time it
obtains the privileges (not supported).
Bits 23 to 16—Minimum Latency Specification (MGNT 7 to 0): Specify the burst interval
required by the PCI device (not supported).
Bits 15 to 8—Interrupt Pin Specification (IPIN7 to 0)
Bits 15 to 8:
IPIN7 to 0
H'01
H'02
H'03
H'04
H'05 to H'FF
Description
INTA used
INTB used
INTC used
INTD used
Reserved bits
(Initial value)
Bits 7 to 0—Interrupt Line Specification (ILIN7 to 0): Specifies an interrupt line of a system to
which interrupt output used by the PCIC is connected.
Rev.4.00 Oct. 10, 2008 Page 878 of 1122
REJ09B0370-0400