SH7751 Datasheet, PDF (289/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Instruction Set
7.2 Addressing Modes
Addressing modes and effective address calculation methods are shown in table 7.1. When a
location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated
into a physical address. If multiple virtual memory space systems are selected (MMUCR.SV = 0),
the least significant bit of PTEH is also referenced as the access ASID. See section 3, Memory
Management Unit (MMU).
Table 7.1 Addressing Modes and Effective Addresses
Addressing Instruction
Mode
Format
Register
Rn
direct
Register
indirect
@Rn
Effective Address Calculation Method
Effective address is register Rn.
(Operand is register Rn contents.)
Effective address is register Rn contents.
Rn
Rn
Register
indirect
with post-
increment
@Rn+
Effective address is register Rn contents.
A constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand, 8 for a
quadword operand.
Rn
Rn
Rn + 1/2/4/8 ₊
1/2/4/8
Register
indirect
with pre-
decrement
@–Rn
Effective address is register Rn contents,
decremented by a constant beforehand:
1 for a byte operand, 2 for a word operand,
4 for a longword operand, 8 for a quadword
operand.
Rn
Rn – 1/2/4/8 _–
Rn – 1/2/4/8
1/2/4/8
Calculation
Formula
—
Rn → EA
(EA: effective
address)
Rn → EA
After
instruction
execution
Byte:
Rn + 1 → Rn
Word:
Rn + 2 → Rn
Longword:
Rn + 4 → Rn
Quadword:
Rn + 8 → Rn
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
Quadword:
Rn – 8 → Rn
Rn → EA
(Instruction
executed
with Rn after
calculation)
Rev.4.00 Oct. 10, 2008 Page 191 of 1122
REJ09B0370-0400