SH7751 Datasheet, PDF (227/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
occurs during address translation, or the comparison shows a mismatch, an exception is not
generated, no operation is performed, and the write is not executed. If a data TLB multiple hit
exception occurs during address translation, processing switches to the data TLB multiple hit
exception handling routine.
31
24 23
Address field _{1 1 1 1 0 1 0 0}
31
Data field
Tag
15 1413
Way
Entry
10 9
543210
A
210
UV
Legend:
V: Validity bit
U: Dirty bit
A: Association bit
: Reserved bits (0 write value, undefined read value)
Figure 4.14 Memory-Mapped OC Address Array
4.6.4 OC Data Array
The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The way and entry to be accessed are specified in the address field, and
the longword data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F5 indicating the OC data array, the way is
specified by bit [14], and the entry is specified by bits [13:5]. CCR.OIX has no effect on this entry
specification. The OC address array access in RAM mode (CCR.ORA = 1) is performed only to
cache, and bit [13] specifies the way. For details on address allocation, see section 4.6.5, Summary
of Memory-Mapped OC Addresses. Address field bits [4:2] are used for the longword data
specification in the entry. As only longword access is used, 0 should be specified for address field
bits [1:0].
The data field is used for the longword data specification.
The following two kinds of operation can be used on the OC data array:
Rev.4.00 Oct. 10, 2008 Page 129 of 1122
REJ09B0370-0400