SH7751 Datasheet, PDF (214/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
Workarounds: When RAM mode is specified in cache enhanced mode, either of the following
workarounds can be used to avoid the problem.
Workaround 1:
Use only 8 Kbytes of the 16-Kbyte internal RAM area. In this case, RAM areas for which
address bits [12:0] are identical and only bit [13] differs must not be used. For example,
the 8-Kbyte RAM area from H'7C000000 to H'7C001FFF or from H'7C001000 to
H'7C002FFF may be used.
Note:
When a break is used to swap instructions by a debugging tool, etc., a memory access
address may be changed when an instruction following the instruction generating the
break is swapped for another instruction, causing the unused 8-Kbyte RAM area to be
accessed. This will result in the problem described above. However, this phenomenon
only occurs during debugging when a break is used to swap instructions. Using a break
with no instruction swapping will not cause the problem.
Workaround 2:
Ensure that there are no instructions that generate an interrupt or exception within four
instructions after an instruction that accesses internal RAM. For example, the internal
RAM area can be used as a data table that is accessed only by load instructions, with
writes to the internal RAM area only being performed when the table is generated. In this
case, set SR.BL to 1 to disable interrupts while writing to the table. Also take measures to
ensure that no exceptions due to TLB misses, etc., occur while writing to the table.
Note: The problem still may occur when a break is used to swap instructions by a debugging
tool. This phenomenon only occurs during debugging when a break is used to swap
instructions. Using a break with no instruction swapping will not cause the problem.
4.4 Instruction Cache (IC)
4.4.1 Configuration
The instruction cache consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32-
byte data (16 instructions). The instruction cache in the SH7751R adopts the 2-way set-associative
method, and each way consists of 256 cache lines.
Rev.4.00 Oct. 10, 2008 Page 116 of 1122
REJ09B0370-0400