SH7751 Datasheet, PDF (542/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between
an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the
DMAC, to provide faster access to synchronous DRAM. As synchronous DRAM is internally
divided into two or four banks, after a READ or WRIT command is issued for one bank it is
possible to issue a PRE, ACTV, or other command during the CAS latency cycle or data latch
cycle, or during the data write cycle, and so shorten the access cycle.
When a read access is followed by another read access to the same row address, after a READ
command has been issued, another READ command is issued before the end of the data latch
cycle, so that there is read data on the data bus continuously. When an access is made to another
row address and the bank is different, the PRE command or ACTV command can be issued during
the CAS latency cycle or data latch cycle. If there are consecutive access requests for different row
addresses in the same bank, the PRE command cannot be issued until the last-but-one data latch
cycle. If a read access is followed by a write access, it may be possible to issue a PRE or ACTV
command, depending on the bank and row address, but since the write data is output at the same
time as the WRIT command, the PRE, ACTV, and WRIT commands are issued in such a way that
one or two empty cycles occur automatically on the data bus. Similarly, with a read access
following a write access, or a write access following a write access, the PRE, ACTV, READ, or
WRIT command is issued during the data write cycle for the preceding access; however, in the
case of different row addresses in the same bank, a PRE command cannot be issued, and so in this
case the PRE command is issued following the number of Trwl cycles specified by the TRWL bits
in MCR, after the end of the last data write cycle.
Figure 13.34 shows a burst read cycle for a different bank and row address following a preceding
burst read cycle.
Pipelined access is enabled only for consecutive access to area 3, and will be discontinued in the
event of an access to another area. Pipelined access is also discontinued in the event of a refresh
cycle, or bus release due to bus arbitration. The cases in which pipelined access is available are
shown in table 13.16. In this table, “DMAC dual” indicates transfer in DMAC dual address mode,
and “DMAC single”, transfer in DMAC single address mode.
Rev.4.00 Oct. 10, 2008 Page 444 of 1122
REJ09B0370-0400