SH7751 Datasheet, PDF (676/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
Four requests can be queued
Handshaking is necessary
to send additional requests
CKIO
1st 2nd 3rd 4th
5th
DBREQ
BAVL
TR
A25–A0
D31–D0
RAS, CAS,
WE
TDACK
ID1, ID0
CA
CA
CA
CA
D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2
RD
RD
RD
RD
Must be ignored
(no request transmitted)
Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2
Rev.4.00 Oct. 10, 2008 Page 578 of 1122
REJ09B0370-0400